The present invention relates, in general, to testing of Phase Locked Loops and, more specifically, to a method and circuitry for Built In Self Test (BIST) of Phase Locked Loops incorporated into integrated circuits.
Phase locked loops (PLLs) are used in many electronics applications. Some are used to derive a synchronous clock signal from serial data, some are used to derive a higher frequency synchronous clock signal from a lower frequency clock, and some are used to generate a delayed clock signal whose phase is aligned to a clock signal with the same frequency. PLLs are used in many digital integrated circuits, but are partially analog or mixed-signal in nature. Their performance is thus non-deterministic and testing them in a manufacturing environment can often be time-consuming or inadequate, especially if only conventional synchronous digital tests are used.
The most important PLL parameters which are typically tested include lock time, lock range, phase jitter, phase error, and the induced bit error rate (BER). As is done for most mixed-signal functions, these parameters are typically measured functionally, i.e. by applying stimulus that the PLL would be subjected to in the target application and measuring its response. These tests can be time-consuming to create. require long test times, and require high precision testers. For example, lock range is typically measured, after phase lock has been achieved, by gradually increasing or decreasing the stimulus frequency until the phase is no longer locked. This requires a tester with precise control of signal transition timing. BER is measured over extended periods of time (minutes or hours), or else a low-level signal with a precise amplitude is used to induce an increased BER. This requires a tester with precise output voltages, possibly at high frequencies.
It is an object of this invention to provide a circuit and method for testing PLLs in a way which is comparable to tests which are typically used, but in a way which is simple enough to economically include within an integrated circuit containing the PLL and thus facilitate built-in self-test (BIST). The BIST circuit described herein is connected only to the normal input and output signals of the PLL, hence does not interfere with internal circuitry, does not affect the normal capabilities of the PLL, and does not depend on whether the PLL""s internal operation is digital or analog. This contrasts significantly with, for example, U.S. Pat. No. 5,295,079 by Hee Wong et al, which requires several connections to the internal circuitry of the PLL, and in a way which is very dependent on the exact nature of the PLL.
To test a PLL, the new BIST circuit described herein is connected to the PLL and an input stimulus clock with mid-range frequency for the PLL is also connected. The BIST circuit provides a substitute clock input derived from the PLL output clock and has the same phase and frequency as the stimulus clock to the PLL. When the circuit is enabled, the PLL continues to generate approximately the same frequency. The feedback clock is then interrupted for one or more cycles. The output frequency of the PLL responds to these missing cycles in a way which is precisely proportional to the product of the loop gain and the loop bandwidth for the PLL. The change in frequency is easily measured using conventional means, on-chip. The loop Gain Bandwidth is proportional to the square of the natural frequency, fn, of the PLL. fn is an important PLL design parameter.
The lock range of the PLL. is measured similarly to the above procedure, except that the derived signal is continuously interrupted, causing the output frequency of the PLL to continuously decrease until it reaches its lowest possible frequency. This frequency is measured using conventional means, and is equal to the lowest frequency within the lock range of the PLL. A similar procedure leads to the highest frequency. When the lowest or highest frequency is attained, the stimulus clock is reconnected and the time to attain phase lock is measured by counting clock pulsesxe2x80x94this give the lock time.
The jitter within the PLL is measured by connecting an edge-triggered latch between the input clock and the output clock and determining the amount of delay which must be added to or removed from the clock signal to ensure that the output of the latch is a predictable series of ones and zeroes.
For a receiver whose data clock is generated from the received data, the BER is predicted by testing the BER for various, precisely added phase offsets. When the phase offset becomes large relative to the normal offset, the BER becomes much worse than normal and can be measured in a much shorter time.
Knowing several exact phase offsets and resulting BERs, the BER can be predicted for zero phase offset. A problem with this approach has been the difficulty in generating small and precise increments in phase xe2x80x94 the method of the present invention achieves the needed precision.